Additive Resource Scaling in Quantum Circuits for Search in Cryptanalysis
Published in ISCAS 2026, Shanghai, China, 2026
Recommended citation: L. Lavagna, G. Vittori, A. Rosato and M. Panella, "Additive Resource Scaling in Quantum Circuits for Search in Cryptanalysis," 2026 IEEE International Symposium on Circuits and Systems (ISCAS), Shanghai, China, 2026, pp. 2758-2762 [https://ieeexplore.ieee.org/document/11562218](https://ieeexplore.ieee.org/document/11562218)
Quantum search algorithms are often analyzed in idealized, isolated models, yet real hardware and cryptanalytic applications involve communication channels and residual entanglement. We develop a unified circuit framework that models these effects explicitly, introducing a controllable quantum-channel interaction between system and environment registers. The resulting non-isolated circuits exhibit additive time-space behavior, instead of standard multiplicative scaling. We provide circuit schematics, simulation data, and performance visualization demonstrating how a single-qubit environment modifies Grover oscillations and success probability trajectories of cryptographic attacks. The proposed framework connects algorithmic tradeoffs with measurable circuit phenomena, offering a practical methodology for quantum-classical hybrid circuits design.